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?1 cxd2053am/as e96531-st auto wide, edtv- ii id detection, id-1 detection description the cxd2053am/as is an ic which has the three functions of identifying the wide video (auto wide), detecting the edtv- ii id, and detecting id-1 (eiaj, cpx1024) from the video signal. features video aspect ratio identification used with wide tvs is realized with a single chip. i 2 c bus interface. this ic can also be used without the bus. for auto wide function, 525/60 (ntsc) and 625/50 (pal, secam) can be supported. applications wide tv structure silicon gate cmos ic block diagram absolute maximum ratings supply voltage v dd v ss ?0.5 to +7.0 v input voltage v i v ss ?0.5 to v dd + 0.5 v output voltage v o v ss ?0.5 to v dd + 0.5 v storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage v dd 4.5 to 5.5 v operating temperature topr ?0 to +70 ? sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxd2053as 28 pin sdip (plastic) i 2 c bus interface vsin vdin adin mcon oed olbx o164 oaw2 sda xi oaw1 scl xo data slice sync separator ad converter auto wide identification edtv- ii id decoder timing signal generator id-1 decoder 21 22 19 24 25 26 27 28 15 16 2 11 10 cxd2053am 28 pin sop (plastic)
?2 cxd2053am/as pin description pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 av dd adin av ss cpv vrb vrt ccp iset av dd vsin vdin av ss tst1 tst2 scl [eddec2] sda [ed2fsc] v ss xrst mcon v dd xo xi v ss olbx o164 oaw1 oaw2 oed i i i i i i i i i i i i/o i i o i o o o o o analog analog analog analog analog analog analog analog analog analog ttl * 2 ttl * 2 cmos * 1 cmos * 1, 3 ttl * 1 ttl cmos cmos cmos cmos cmos cmos cmos analog power supply. ad converter input. analog ground. clamp voltage. ad converter bottom voltage. ad converter top voltage. ad converter clamp integrating capacitor connection. bias current setting. analog power supply sync separation input. data slicer input. analog ground. test input; connect to v ss . test input; connect to v ss . i 2 c bus clock [edtv- ii decoding identification switching] i 2 c bus data [edtv- ii 3.58 m check existence] digital ground. reset at 0. i 2 c bus-free mode switching; 0 = i 2 c-free. digital system power supply. oscillator connection (14.318mhz). oscillator connection or clock input. digital ground. vb-id detection output; 1 = letter-box, 0 = normal. vb-id detection output; 1 = full mode. auto wide identification output; 1 = wide video subtitles not present. auto wide identification output; 1 = wide video subtitles present. edtv- ii id bit 3 detection output. symbol i/o i/o level description * 1 schmitt input * 2 with pull-down resistor * 3 open drain note) in i 2 c-free mode when pin 19 (mcon) = 0, pins 15 and 16 switch to the functions in parentheses [ ].
?3 cxd2053am/as electrical characteristics dc characteristics (logic section) (v dd = 5.0v, v ss = 0v, ta = 25?) item output voltage output voltage output voltage input voltage input voltage input voltage input hysteresis width input leak current output leak current input current feedback resistor current consumption v oh v ol v oh v ol v ol v ih v il v ih v il v ih v il vhys ii i oz ii rfbk i dd i oh = ?ma i ol = 4ma i oh = ?ma i ol = 3ma i ol = 3ma v in = either v ss or v dd v in = eother v ss or v dd v in = v dd xi (pin 22) = either v dd or v ss clock 14.318mhz v dd ?0.8 v dd /2 2.2 0.7 v dd 0.8 v dd 0.05 v dd ?0 ?0 40 250k 0.4 100 1m 29 0.4 v dd /2 0.4 0.8 0.3 v dd 0.2 v dd +10 +40 240 2.5m v v v v v v v v v v v v v ? ? ? ma pins 24, 25, 26, 27 and 28 pin 21 only pin 16 only pins 13, 14, 18 and 19 pin 22 only pins 15 and 16 pins 15 and 16 pin 18 except for pins 13, 14 and 22 pin 16 only pins 13 and 14 between pins 21 and 22 sum of pins 1, 9 and 20 symbol condition min. typ. max. unit remarks item clock frequency fxi 14.318 mhz pin 22 input, or oscillator between pins 21 and 22 symbol condition min. typ. max. unit remarks ac characteristics (v dd = 5.0v, v ss = 0v, ta = 25?) item input pin capacitance output pin capacitance input/output pin capacitance c in c out c i/o v dd = v i = 0v, f = 1mhz v dd = v i = 0v, f = 1mhz v dd = v i = 0v, f = 1mhz 9 11 11 pf pf pf symbol condition min. typ. max. unit remarks i/o pin capacitance
?4 cxd2053am/as pins and electrical characteristics analog section (v dd = 5.0v, v ss = 0v, ta = 25?) pin no. 1 3 2 4 5 6 7 av dd av ss adin cpv vrb vrt ccp symbol equivalent circuit description ad converter analog power supply. connect a low-noise power supply from the digital system. ad converter analog ground. connect to the same potential as other v ss and av ss . ad converter input. this pin is pedestal clamped to the potential of cpv (pin 4), so input the video signal with capacitor coupled. adin (pin 2) pedestal clamp voltage setting. ad converter input range setting. the resistor between pins 5 and 6 is 310 (typ.). clamp circuit integrating capacitor connection. connect 0.022f between this pin and av ss (pin 3). not connected to v dd (pin 20) or av dd (pin 9) inside the ic. not connected to v ss (pins 17 and 23) or av ss (pin 12) inside the ic. av ss av dd 2 av ss av dd 4 av ss av dd 5 av ss av dd 6 av ss av dd 7
?5 cxd2053am/as 9 12 8 10 av dd av ss iset vsin sync separation system analog power supply. connect a low-noise power supply from the digital system. sync separation system analog ground. connect to the same potential as other v ss and av ss . bias setting. connect to av dd (pin 9) with 33k . chip clamp, sync separation input. input with capacitor coupled. pedestal clamp, id-1 data slicer input. input with capacitor coupled. not connected to v dd (pin 20) or av dd (pin 1) inside the ic. not connected to av ss (pin 3) or v ss (pins 17 and 23) inside the ic. av ss av dd 8 av ss av dd 10 11 vdin 11 av ss av dd clamp voltage 1.5v clamp voltage 1.5v pin no. symbol equivalent circuit description
?6 cxd2053am/as 1. description of auto wide function the auto wide function performs wide screen identification from the black bands at the top and bottom of the screen. as shown below, the cxd2053am/as identifies the three types of 4:3 normal video, 16:9 wide video, and wide video with subtitles. 4:3 normal video 16:9 wide video wide video with subtitles fig. 1. wide identification types the results of this auto wide identification are expressed by 2 bits, and are output through the i 2 c bus during bus mode. also, these results are output directly to the oaw1 (pin 26) and oaw2 (pin 27) pins regardless of bus or bus-free mode. auto wide identification is provided with a transition time of about 1 to 15 seconds to prevent misoperation. during i 2 c bus mode, wide identification can be changed quickly without this transition time by manipulating the inst bit. 2. description of id-1 (transmitter method of additional video information, aspect ratio identification) as shown in the table below, the additional video information consists of 14-bit data, to which a 6-bit crcc is appended for a total of 20 bits. on an ntsc video signal, this information is carried on lines 20 and 283 of the vertical blanking interval. bit-no word0 word1 word2 description "1" "0" a b 1 2 3 transmitter aspect ratio pictorial representation format undefined full mode (16:9) letter-box 4:3 normal discrimination information about the video signal and any other signal (audio signal, etc.) incident to the video and transmitted simultaneously. word 0 dependent discrimination signal word 0 dependent discrimination signal, information, etc. 4 5 6 4-bit width 4-bit width (from the provisional standard of eiaj, cpx-1204) table 1. description of id-1 signal of the 14-bit data noted above, only the first 2 bits are handled by the cxd2053am/as. these 2 bits are obtained by the i 2 c bus during bus mode. also, these bits are output directly to the olbx (pin 24) and o164 (pin 25) regardless of bus or bus-free mode.
?7 cxd2053am/as 3. description of edtv- ii id as shown in the table below, edtv- ii id consists of 27-bit data. on an ntsc video signal, this information is carried on lines 22 and 285 of the vertical blanking interval. bit no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 reference signal reference signal letter-box parity of bits 3 and 5 undefined field no. multiphase vt vh hh hh precombing broadcasting station operation bit broadcasting station operation bit broadcasting station operation bit 0 full line 0 0 1 a no no no no 1 letter-box 1 2 b yes yes yes yes 15 16 17 18 19 20 21 22 23 24 25 26 27 undefined undefined undefined error correction signal error correction signal error correction signal error correction signal error correction signal error correction signal 0 confirmation sine wave confirmation sine wave confirmation sine wave 0 description 01 bit no. description 01 table 2. description of edtv- ii id (discrimination control signal) signal of the 27 bits noted above, the cxd2053am/as outputs only bits 3 and 5. these 2 bits are obtained by the i 2 c bus during bus mode. also, bit 3 only is output directly to the oed (pin 28) regardless of bus or bus-free mode. since the cxd2053am/as does not perform decode processing for bits 6 to 23, this results in simple identification which does not use the error correction signals. 4. clock the cxd2053am/as requires a 4fsc clock (14.318mhz). connect xi (pin 22) and xo (pin 21) when using a crystal oscillator. when inputting the clock from an external source, input to xi (pin 22). clock is 14.318mhz regardless of switching auto wide 525/60 (ntsc) or 625/50 (pal, secam). 5. settings and data input/output the cxd2053am/as settings and data input/output can be performed by direct setting by pins or with the i 2 c bus interface.
?8 cxd2053am/as 5-1. i 2 c bus settings and data can be taken out via the i 2 c bus when mcon (pin 19) is set to "1". this lsi supports the i 2 c bus slave receiver and slave transmitter modes. the slave address is 1c (h). also, in addition to standard mode (max. 100k bit/s), this lsi also supports high-speed mode (max. 400k bit/s). even when the ic power supply falls to 0v, it does not occupy the bus. however, the absolute maximum ratings should be strictly observed. the i 2 c bus transfer sequence is shown in the figure below. the amount of data transferred by this ic is 2 bytes for the write (receiver) side and 1 byte for the readout (transmitter) side. data write (receiver mode) sm slam 7654321 0 1 76543210 1 1 76543210 wm as datam as datam as p sm slam 7654321 0 1 76543210 1 rm as datas xam p data readout (transmitter mode) symbol * m * s s p sla data w r a xa from master to slave from slave to master start condition stop condition slave address data 0: write master ? slave 1: read slave ? master clock pulse for acknowledgement (sda: l) acknowledgement none (sda: h) description
?9 cxd2053am/as table 3. list of i 2 c bus controls r/w wr rd bit bit 7 msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lsb bit 7 msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lsb bit 7 msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lsb ed2fsc ed2res eddec1 eddec2 vblnj1 vbres awres inst no use and test uparea pal ed2id edvld vbid vbvld aws 0 when checking the 3.58mhz amplitude during edtv- ii id decoding; 1 when not checking the amplitude. edtv- ii id decoding function reset. 1 = reset. edtv- ii id decoding function detection switching. standard values: bit 5 = 0, bit 4 = 1. edtv- ii id decoding function detection switching. standard values: bit 3 = 0, bit 2 = 1. decoding not only of line 20 but also of the 1 line before and after line 20 by the id-1 decoding function. 0 = yes, 1 = line 20 only. id-1 decoding function reset. 1 = reset. auto wide function reset. 1 = reset to 4:3. auto wide switching is performed without the wait time by changing inst from 0 to 1. not used and lsi test bits. be sure to set all bits to 0. normally. set the same value as that of pal bit below. when pal = 0, uparea = 0, etc. auto wide function switching. 525/60 when pal = 0 and 625/50 when pal = 1. edtv- ii id decoding results. 3rd bit of the edtv- ii id. edtv- ii id decoding results. 5th bit of the edtv- ii id. edtv- ii id decoding results judgment. becomes 1 when a valid edtv- ii id exists. the above noted ed2id is output and held regardless of this judgment. id-1 decoding results. 1st bit: full mode bit. id-1 decoding results. 2nd bit: letter-box bit. vb-id decoding results judgment. becomes 1 when a valid vb-id exists. the above noted vb-id is output and held regardless of this judgment. auto wide identification results. for 4:3 video, bit 1 = 0 and bit 0 = 0. for 16:9 wide video, bit 1 = 0 and bit 0 = 1. for subtitle video, bit 1 = 1 and bit 0 = 0. name description 1st byte 2nd byte 1st byte
?10 cxd2053am/as 5-2. bus-free mode the cxd2053am/as can be operated without using the i 2 c bus when pin 19 (mcon) is set to 0 and the ic is switched to bus-free mode. in this case, the contents normally set by the i 2 c are fixed to the values below. also, only the two functions listed in the table below can be switched by pins 15 (scl) and 16 (sda). bit bit 7 msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lsb bit 7 msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lsb ed2fsc ed2res eddec1 eddec2 vblnj1 vbres awres inst no use and test uparea pal directly controlled by pin 16 (sda). the unmodified sda pin level becomes ed2fsc. ed2res = 0 bit5 = 0, bit4 = 1. directly controlled by pin 15 (scl). when scl = 0, bit 3 = 0 and bit 2 = 1. when scl = 1, bit 3 = 1 and bit 2 = 0. vblnj1 = 0 vbres = 0 awres = 0 inst = 0 all 0 uparea = 0 pal = 0 fixed to 525/60 mode. name description 1st byte 2nd byte i 2 c setting information table 4. setting values during bus-free mode (pin 19 (mcon) = 0)
?11 cxd2053am/as 6. processing of edtv- ii id and id-1 data from the bus edtv- ii id or id-1 edvld or vbvld decoder data validity judgment i 2 c cxd2053am/as pin direct output to microcomputer as shown in the figure above, the data validity judgment and decoding results are obtained independently during edtv- ii id or id-1 decoding. when outputting these results directly to pins, the results are output after first taking their logical product (and). these results are output independently to the i 2 c bus. therefore, processing inside the microcomputer which has acquired the information from the i 2 c is performed either by simply outputting this data directly to the pins or by taking the logical product (and) as above. in addition, performing the processing when the data validity judgment result (edvld or vbvld) is 1 and the decoding result is 0 allows video to be judged as 4:3 video. even video which has had the top and bottom of the screen blacked out due to picture composition intentions can be viewed as the original 4:3 video by giving this judgment priority over the auto wide function. 7. setting edtv- ii id decoding function the performance of the edtv- ii id decoding function can be switched directly by pin settings during either i 2 c bus or bus-free mode. setting i 2 c exists i 2 c -free resistance to ghosting resistance to weak electric fields ed2fsc = 0 eddec2 bit3 = 0, bit2 = 1 scl (15pin) = low sda (16pin) = low medium medium ed2fsc = 0 eddec2 bit3 = 1, bit2 = 0 scl (15pin) = high sda (16pin) = low strong medium ed2fsc = 1 eddec2 bit3 = 1, bit2 = 0 scl (15pin) = high sda (15pin) = high strong strong table 5. edtv- ii id decoding function switching ed2fsc is originally a function which stops the 3.58mhz amplitude check for the y signal input from the s terminal, etc. however, it can also be used in combination with the eddec2 setting to increase the resistance to ghosting and weak electric fields as shown in the table above. eddec2 is the luminance check level switching during the 3.58mhz or 2.04mhz confirmation signal interval. similarly, although eddec1 is the 2.04mhz amplitude check level switching, it should be set to bit 5 = 0 and bit 4 = 1. since edtv- ii id identification for this ic is simple identification, increasing the resistance to weak electric fields, etc. results in a tradeoff which increases the possibility of misoperation. accordingly, the leftmost settings in the table above should be used as the standard settings, and other settings used only when necessary.
?12 cxd2053am/as 8. judgment time during auto wide and shortening this time an appropriate judgment transition wait time is provided during auto wide in order to prevent misjudgments. during i 2 c bus mode, this transition time can be shortened as necessary using the inst bit. at the rising edge of inst, the screen changes without waiting to the screen being judged at that time. the inst pulse width should be set to 3 fields or more as shown below. 3 fields (50ms) or more inst the wait time-free status ends with the auto wide judgment transition or when inst becomes 0. this situation is illustrated in the figure below. inst wait time-free status (inside the ic) auto wide identification transition time wait inst wait time-free status (inside the ic) auto wide identification no screen change the screen change here. inst does not function. after transition transition time wait
?13 cxd2053am/as application circuit 33k 100 0.01 0.01 60 to 80ma v dd = 5.0v 5% 2.2k 100 33 15 10 3.3k 10k v in 100 100 10 1 100 10 1000p 0.1 100 100 ire 0 ire ?0 ire 0.022 470p direct output (open when not used) i 2 c 22p 22p 14.3mh z av ss av ss iset vrt cpv vrb ccp vsin vdin adin mcon xrst oed olbx o164 oaw2 sda xi tst1 oaw1 scl tst2 xo v ss v ss 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 9 20 1 2.0vp-p 100 av dd av dd v dd cxd2053am/as application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?14 cxd2053am/as package outline unit: mm cxd2053am sony code eiaj code jedec code sop-28p-l04 package structure package material lead treatment lead material package weight 42 alloy solder plating epoxy / phenol resin 28pin sop (plastic) 375mil 18.8 ?0.1 + 0.4 15 28 0.45 0.1 1.27 9.3 2.3 ?0.15 + 0.4 0.1 ?0.05 + 0.2 0.5 0.2 0.2 ?0.05 + 0.1 7.6 ?0.1 + 0.3 10.3 0.4 14 0.15 m 0.12 * sop028-p-0375-d 1 0.7g cxd2053as 28pin sdip (plastic) 400mil 26.9 ?0.1 + 0.4 8.5 + 0.3 ?0.1 0.25 + 0.1 ?0.05 28 15 114 1.778 10.16 0?to 15 3.7 + 0.4 ?0.1 0.5 0.1 0.9 0.15 3.0 min 0.5 min sony code eiaj code jedec code package structure package material lead treatment lead material package weight epoxy resin solder plating copper / 42 alloy sdip-28p-01 sdip028-p-0400-a 1.7g

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